Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

RAM uninferred due to asynchronous read logic

Hello, I have a cache module which uses an inferred synchronous RAM block. When I synthesize the module by itself (as the project's top module) the synthesis works as intended and the RAM is in...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Hello again,

In my original code (the code that failed) the uninferred RAM data output was connected straight to the address input of a different RAM block. Can this be the source of the trouble? The problem disappeared when I inserted a layer of logic between data output and address input.

This is the only difference I can think of between this and many other designs in which I used this inferred RAM construct witl Quartus-2. I don't remember seeing this case mentioned in the manual but I'll have to check again more carefully...

I will conduct an experiment and post the result ASAP.