Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

RAM uninferred due to asynchronous read logic

Hello, I have a cache module which uses an inferred synchronous RAM block. When I synthesize the module by itself (as the project's top module) the synthesis works as intended and the RAM is in...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Hello,

As you suggested, I have just tried registering the read address instead of the output, but it does not help.

I had seen that construct you mention suggested in the manual (example 10-4 in the handbook, section on recommended hdl coding styles), so this is one of the things that I tried previously. Yet, the template in Quartus-2 'insert template' menu (and in some other Altera manuals that I don't have on hand right now) matches the construct I have used. I will for the sake of consistency refactor the RAMs to use the recommended construct (it is compatible with ISE too) but as I said it does not help in this case.

I think you are right in that some of the logic connected to the RAM output somehow gets mixed in with the RAM construct and upsets the 'pattern' recognized by the synthesis tool. Putting the extra layer of logic I mentioned in my previous post prevents that 'mixing'.

If there is a synthesis option to prevent optimization across hierarchy boundaries, it might help. I haven't found it in the IDE or the manual (yet).

Thank you very much for your help!