RAM uninferred due to asynchronous read logic

Did you notice, that the Quartus template is using a different topology than your design? It's registering the read address rather than the output. This structure is corresponding to the actual hardware behaviour. Normally, Quartus is able to convert the output register you have defined in your code into an input register, but apparently this doesn't work in your full design. I guess, that the compiler pushes the register into the design part driven by the RAM before it starts to process the RAM part.