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Altera_Forum
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15 years ago

RAM uninferred due to asynchronous read logic

Hello, I have a cache module which uses an inferred synchronous RAM block. When I synthesize the module by itself (as the project's top module) the synthesis works as intended and the RAM is in...
Altera_Forum's avatar
Altera_Forum
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15 years ago

I have discovered a fix:

If I pass the RAM output through a layer of logic (I have tried an AND gate and a MUX, both implemented as a single LUT I think) then the synthesis works as expected. I guess I should have tried this a lot earlier...

This is a fix I can happily live with so I guess the problem is solved. Yet, I would like to know about that documentation I mentioned in my previous post; knowing how the synthesis works would help me prevent this kind of trouble in the future.

Thank you very much for your help. If you think of some other thing that you'd like me to try, tell me and I will. Or if any of you Altera guys reading this wants the project code to test this issue I can give it to you (with some mild embarrassment about its quality).