RAM uninferred due to asynchronous read logic

I have tried moving the RAM block to a separate module and I get the same result. Synthesizing the module standalone gives the expected result, synthesizing it in my design gives the same error as before.

The separate module in its entirety is this:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.mips_pkg.all;
entity bram_2p is
    generic (
        BRAM_SIZE : integer         := 1024;
        BRAM_WIDTH : integer        := 16
    );
    port(
        clk             : in std_logic;
        reset           : in std_logic;
        rd_addr         : in std_logic_vector(9 downto 0);--in std_logic_vector(log2(BRAM_SIZE)-1 downto 0);
        rd_data         : out std_logic_vector(BRAM_WIDTH-1 downto 0);
        
        wr_addr         : in std_logic_vector(9 downto 0);
        wr_data         : in std_logic_vector(BRAM_WIDTH-1 downto 0);
        
        we              : in std_logic
    );
end entity bram_2p;
architecture inferred of bram_2p is
type t_ram is array(BRAM_SIZE-1 downto 0) of std_logic_vector(BRAM_WIDTH-1 downto 0);
signal ram :                t_ram;
begin
memory:
process(clk)
begin
    if clk'event and clk='1' then
        if we='1' then
            ram(conv_integer(wr_addr)) <= wr_data;
        end if;
    
        rd_data <= ram(conv_integer(rd_addr));
    end if;
end process memory;
end architecture inferred;

I have tried it with and without generics, the code is a bit dirty as the result of a lot of aimless changes.

The code is nearly identical to all the Altera templates I have been able to find, and identical to the code that I have been using with no problem in other projects.

There definitely is something in my code that is confusing the synthesizer but I can't find what it is.

I have a question for any Altera engineers thay may be reading this. Is there an app note or document that explains exactly how inference works? So I can guess under which circumstances it will fail, despite using the Altera template?

I have tried enabling all the error message levels that I have been able to find in the IDE but the only error message is this:

Info: Found 1 instances of uninferred RAM logic
    Info: RAM logic "mips_cache:cache|bram_2p:code_line_memory|ram" is uninferred due to asynchronous read logic

There is no error message involving any of the ram interface signals.

At this point I think we can call this behavior a bug, in fairness. All I want is to find some way to work around it that does not involve instantiating an architecture-dependent module.