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Altera_Forum
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15 years ago

RAM uninferred due to asynchronous read logic

Hello, I have a cache module which uses an inferred synchronous RAM block. When I synthesize the module by itself (as the project's top module) the synthesis works as intended and the RAM is in...
Altera_Forum's avatar
Altera_Forum
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15 years ago

Regarding the RAM inference problem, as we haven't seen the real code, it's only guessing. The requirements for RAM inference are basically simple, but depending on the coding style, it may be more difficult, to see if they are met. In case of doubt, I would use the Altera RAM templates as a starting point.

I can't exclude of course, that there may be a Quartus problem, that prevents RAM inference in cases, that are expected to work. But I'm not aware of any, yet.