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Altera_Forum's avatar
Altera_Forum
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15 years ago

RAM uninferred due to asynchronous read logic

Hello, I have a cache module which uses an inferred synchronous RAM block. When I synthesize the module by itself (as the project's top module) the synthesis works as intended and the RAM is in...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

I am trying to install Quartus 2 10.1 on Kubuntu... a nightmare on its own right. I wonder if the guys at Altera have ever heard of apt-get or Ubuntu... When and if I get the install done I will try my code on it.

As for the partition, I have first to figure what a 'partition' is in this context :) thanks for the tip.

The manual warns you that RAM inference can fail of the RAM output goes straight to a hierarchy boundary (which it does). But I have used this exact same construct in the past with no trouble, and as I said, when you compile the cache module separately (i.e. not connected to a parent module) it works fine.

I will try moving the RAM to a separate module and see if it helps...