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Altera_Forum's avatar
Altera_Forum
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15 years ago

RAM uninferred due to asynchronous read logic

Hello, I have a cache module which uses an inferred synchronous RAM block. When I synthesize the module by itself (as the project's top module) the synthesis works as intended and the RAM is in...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

have you tried it in a newer version of quartus?

I can only think then there is something wrong elsewhere in the code. Have you tried raising a Mysupport request?