RAM uninferred due to asynchronous read logic

Thanks for your reply!

I have tried registering the address (and then reading from the array outside of the synchronous process) and it makes no difference. Even if I do this it still fails:

...
code_line_memory:
process(clk)
begin
    if clk'event and clk='1' then
        if ps=code_refill_bram_1 or ps=code_refill_sram8_3 or ps=code_refill_sram_1 then
            code_line_table(conv_integer(code_word_addr_wr)) <= code_refill_data;
        end if;
        -- register address 
        code_word_addr <= code_rd_addr(11 downto 2);
        code_cache_rd <= code_line_table(conv_integer(code_word_addr));
    end if;
end process code_line_memory;
...

I have tried registering the address in a separate process, just in case I was confusing the synthesizer. Still didn't work.

The only thing that seems to work so far is registering code_cache_rd (that is, registering it again, by loading it on a register). But I can't accomodate an extra delay cycle in my design.

The templates I talk about are those included in Quartus-2 and those shown in the manual (chap. 6 'recommended hdl coding styles'). Both are analogous to the code snippet I posted, i.e. unregistered address and registered output (though the actual hardware implementation may be different, I realize). I mean, my code is almost verbatim from the Quartus-2 manual template:

...
PROCESS (clock)
BEGIN
IF (clock'event AND clock = '1') THEN
IF (we = '1') THEN
ram_block(write_address) <= data;
END IF;
q <= ram_block(read_address);
-- VHDL semantics imply that q doesn't get data
-- in this clock cycle
END IF;
...
END PROCESS;

Note that I don't care about the read-during-write behavior in this design so reading old data is fine.