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Altera_Forum's avatar
Altera_Forum
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15 years ago

RAM uninferred due to asynchronous read logic

Hello, I have a cache module which uses an inferred synchronous RAM block. When I synthesize the module by itself (as the project's top module) the synthesis works as intended and the RAM is in...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Is code_word_addr the output of some other set of logic? It may be complaining because it cant place the read address in a register internal to the ram. The code you posted shows a registered output, rather than a registered read address. All the code templates that altera provides ask for a registered read address.

The read data is then asynchronously read out from the registered read address with optional output registers.