RAM logic not inferred

The problem is, that 3 RAM definition neither have an unconditional address register nor output register operation. desc_wd0 in contrast has an unconditional operated output register and can be inferred.

The basic operation is as follows:

always @(posedge clk)
begin
if (rxch_rd)
  desc_rptr <= desc_rptr + 1;
rxch_dadr <= rxch_vld_i ? desc_dadr] : CSR_dump_adr;
rxch_desc <= desc_wd0];
end

This restriction is due to synchronous RAM hardware properties to my opinion. If it would be possible to do the rxch_vld_i selection on the registered RAM output signal, then RAM inference would work.