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Altera_Forum
Honored Contributor
15 years agoI overlooked the fact that both clocks come from the same PLL. In that case one can set "CLOCKS_ARE_SYNCHRONIZED" to "TRUE" saving a bit on logic resources and decreasing latencies. The 'rdempty' signal going (or staying) inactive tells when to start (or continue) the state machine to 'unpack' the 24 bits into 8 bit packets.