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I agree with the josyb solution.
Run a state machine on the falling edge of the fast clock.
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What ???? Why on earth complicate things with both falling and rasing edges. There is absolutely no need for that.
I agree with Tricky. By far, the simplest solution is to run the whole thing on a single clock (single edge, of course), and use a clock enable.
If for some reason it is still desirable to use the slow clock as well, then it is pretty simple to have a clock enable on the fast clock that is synced to the slow clock. Both clocks are edge aligned because they are just different multiples on the same PLL.
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P.S. How many answers. Your question has triggered the FPGA design people :-)
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Indeed :)
Honored Contributor
