Quick Question - How to event on multiple clocks rising edges?

It's alright I was over complicating things loads, and it appears to be simulating correctly now...

I already had one state machine running from the slow clock, and then the load state machine on the faster clock to load in all 3 bytes from each word.

I just used a signal generated in the first statemachine (that is synchronised to the slow clock) called Load_FIFO to cause the load state machine to move from the IDLE state into loading the firstbyte into the FIFO. I just have to make sure the clock was 4 times the speed not 3, and include a dummy state in the load state machine to compensate for the 1 clock delay in writing each byte....

Seems to be working so far.. but thanks everyone for all their comments...