Forum Discussion
Altera_Forum
Honored Contributor
15 years agoI haven't read all the replies so I may be saying something redundant. Can you attack the problem from a different approach. Suppose all we are really looking for is a moment when the two clocks are both high. Use the faster clock to sample the slower clock. Provide registers for metastability and edge detection. Use the edge detect as the enable for your logic which is driven from the faster clock.
Jake