Quick Question - How to event on multiple clocks rising edges?

I think I am overdesigning what I am trying to do... as I am pretty sure there will be an easier way to do this.

I am clocking into my FPGA some 24-bit parallel data using the first clock that I described.

I was then trying to use a faster clock to control a state machine to multiplex the 24bit data into an 8 bit FIFO.

I originally tried doing this with a clock that was 3x the speed of the original clock, but found that due to the write producing a one cycle delay, my third byte that was written contained the data from the next word appearing at the 24bit parallel input.

To combat this I wanted to use a clock 4x the speed of the original clock to allow the three bytes to be clocked in, and then a dummy byte not being clocked into the FIFO, so that the entire word could be clocked in by the fast clock in one clock cycle of the slower original clock without loosing anything due to the write delay.

However I need the multiplexing to be synchronised with the slow bus aswell as the fast bus so that I capture the entire 24 bit word rather than the second and third byte of a one word, and the first byte of the next.

Thanks for everyones suggestions so far, but being new to VHDL and I feel I may be getting a little lost in it all... please be patient with me, and know that any and all help is greatly appreciated!

What is the easiest way to multiplex these incoming 24bit words into an 8bit FIFO (The 24bit input comes from a 24bit parallel LVDS interface if that helps at all??)