Quick Question - How to event on multiple clocks rising edges?

The problem is, your code doesnt really follow a template quartus can recognise as a real bit of hardware. What you're asking it to do is put '1' on the "Ld_firstbyte" signal only when the clock rises, and then drop back to '0' when the clock is stable again. This is not a register or any real logic. Some fixes:

1. You need rst in the sensitivity list, else reigsters wont reset in simulation unless there is a clock.

2. Remove MULT_CLK from the sensitivity list.

3. Put the MULT clk inside the intRCLK clk tree. What you want is this:

Loader_start_state : process (rst, intRCLK)
begin
  if (rst = '1') then
    Ld_firstbyte <= '0';
  elsif ((intRCLK'EVENT) and (intRCLK = '1') then   --why not use the rising_edge function isntead?
    if(MULT_CLK='1')) then
      Ld_firstbyte <= '1';
    else
      Ld_firstbyte <= '0';
    end if;
  end if;
end process Loader_start_state;

As an asside - using clocks directly for logic is usually a BAD THING.