Quick Question - How to event on multiple clocks rising edges?

Hi Rysc,

I have just been reading one of your older posts (http://www.alteraforum.com/forum/archive/index.php/t-1024.html), and realised that I have not been thinking how this maps to the hardware and actual registers...

I then thought if i use the event and level of the slower clock and just the level of the faster clock then I should be able to sort it out...

e.g.

  
Loader_start_state : process (intRCLK, MULT_CLK)
 begin
 if (rst = '1') then
  Ld_firstbyte <= '0';
 else if ((intRCLK'EVENT) and (intRCLK = '1') and (MULT_CLK='1')) then
   Ld_firstbyte <= '1';
  else
   Ld_firstbyte <= '0';
  end if;
 end if;
 end process Loader_start_state;

But I still get the error:

error (10822): hdl error at lvds_fifo_control.vhd(219): couldn't implement registers for assignments on this clock edge

I have seen this error before when trying to write on rising and falling edges of the same clock, but now I am just using the faster clocks level, so surely this assignment is only made on the rising edge of the intRCLK?

Sorry I am still pretty new to VHDL and struggling a little...