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Hmm, The two different speed clocks are essentially the same clock, but fed through a PLL...The second clock is exactly 4x the speed of the first. I was intending to use when the faster clock and slower clock rise at the same time, to show me where the start of a cycle is.
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This is possible as long as the edges of both clocks are aligned, which depends on the PLL configuration. Use a clock enable for this purpose. But better don't use the slower clock directly as clock enable. Toggle one data signal with the slower clock, and read this signal with the faster one.
However, I would recommend against this until you are more familiar with synchronous designs.
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