questions when upgrade to Quartus Pro

Hi SyafieqS,

I 100% believe and I am going to follow. I am relative new to the Pro and Platform Designer. I need get familiar with the design platform as much as I could, then I start to delete and update. there are two variables, one is that the original design is on 10AX115H2F34E1SG.

I need port it to the Intel Arria 10 GX dev board. it is a 10AX115S2F45E1SG. one is the Quartus will be upgrade to Pro. any mistake in this two stage will make me loss the track.

with the help Adzim, I can compile the design use Pro. once I make progress on the time analysis. I will start to regenerate everything.

Thank you very much for the support.

David

Hi SyafieqS,

I accepted your post as solution, that is from the strategy level, now when I start the operation. the first problem I have is shown in the following screen capture.

jest_top_qsys_0 here is a submodule of jest204b, from parameter you can see the LMF is 16, 4, 2. when I create a new jest_top. the Maximum L value is 8. the problem is that I couldn't find the jest_top_qsys_0.qsys in the project. from the detail screen capture, the author is unknown, and all description are none. I hope I can have a little bit more detail besides the strategy in this special case.

there is only one sub-directory called synth in directory

C:\FPGA_std18\TSWJ57\Orig\ip\jesd204b\jesd_top_qsys_10

almost all files in synth are .sv file.

seems I need re-generate a new .qys called jesd_top_qsys_10, but I lost the track of this module, even the project compile successfully.

Appreciate your help.

David