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Altera_Forum
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12 years ago

Questions about clock group in timing constrain

I have a question about clock group. Assume in a design, there are two clocks: clk1 and clk2. They are outputs of a PLL. There are no data paths between clk1 and clk2, that means no signals...
Altera_Forum's avatar
Altera_Forum
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12 years ago

Thanks very much, Rysc. If I have other related questions later, I will post here.