Questions about clock group in timing constrain

Altera's dual-clock FIFO has false paths embedded into it. (You'll note in the begining of the TimeQuest mesages one that says, "Reading embedded .sdc constraints..." and if you expand it you'll find them in there.) So in that case you don't have to do anything. If you were using your own FIFO, then yes you would need to cut them, either at the clock level with set_clock_groups or at the path level.