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People send signals across asynchronous domains quite a bit. Often it's just a "slow" signal, like status bit or something like that. Sometimes they're even constants, like signals that set modes of the design out of configuration. They also often try faster transfers and might do some hand-shake logic or something like that. If you can keep it so no paths exist or they all go through FIFOs, good for you.
(In fact, one reason people don't cut timing between unrelated domains is that they often show up as timing failures. For example, if clk1 were clk2 had no relationship, the default setup relationship might be some small number, like 1ps. Then if the a designer accidentally added a path between the domains, it would fail timing and they'd see their mistake right away.
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Thanks, Rysc. I think I got what you mean. In most cases, the data paths between two async clocks may not be real path used to transfer "data: signals, they may be path that transfer control, status signals as you mentioned.
However, in the case I mentioned that FIFO with two different read and write clocks, in this case, is this a data path between these two clocks? Do I need to define clock groups or set false path for these two clocks?
Thanks very much.
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