Questions about clock group in timing constrain

People send signals across asynchronous domains quite a bit. Often it's just a "slow" signal, like status bit or something like that. Sometimes they're even constants, like signals that set modes of the design out of configuration. They also often try faster transfers and might do some hand-shake logic or something like that. If you can keep it so no paths exist or they all go through FIFOs, good for you.

(In fact, one reason people don't cut timing between unrelated domains is that they often show up as timing failures. For example, if clk1 were clk2 had no relationship, the default setup relationship might be some small number, like 1ps. Then if the a designer accidentally added a path between the domains, it would fail timing and they'd see their mistake right away.