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Altera_Forum's avatar
Altera_Forum
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7 years ago

QUESTION on Signal Assignment of same signal and measuring times in FPGA.

Dear all, can you tell me if the following is an illegal statement in VHDL 2008. I want to count up a signal read_pointer synchronously but I am not sure if the signal assignment of the same signa...
Altera_Forum's avatar
Altera_Forum
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7 years ago

This post has no VHDL 2008 code, unless you are using numeric_std_unsigned or numeric_bit_unsigned to allow the addition of a vector and a bit/std_logic (that you are doing in the code) (but I dont think quartus supports those libraries yet).

This is really a question of logic, rather than code standard, and I think Alex has covered it.