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Why does always block get triggered when there are no posedges?
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Most likely because your 'a' signal is being connected to the reset (aclr) signal of the register, and that signal is not edge sensitive, it is level sensitive.
Why would Quartus do such a thing? Because of what FvM wrote above.
Quartus knew you didn't really want that, and gave you some messages to that effect (combinatorial loop and latches for your adder?).
If you care to learn more first hand, reduce your code to it's most simplest case and study the Post-fit netlist for each case (broken vs. working) and you'll see how such a simple thing as the signal's relative priority can have drastic impact on what you get.
Honored Contributor
