Question on posedge in always block

Thanks for your replies.

I have been winging it with verilog for a while now. Normally I stick to just using clock and reset in the sensitivity list (or just clock), however I was trying to copy a bit of Altera's code from their altsmi_parallel application note.

always @ (posedge asmi_write_n, posedge reset_logic)

begin

if (reset_logic)

flash_addr <= flash_start_add;

else

begin

if (asmi_write_n)

flash_addr <= flash_addr + 24'h000001;

else

flash_addr = flash_addr;

end

end

I stuck the reset up front on my code and everything now works.

I am still a bit confused about posedge though. i.e. Why does always block get triggered when there are no posedges?