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Altera_Forum's avatar
Altera_Forum
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14 years ago

question about VHDL code

Hi guys, I am wondering what circuit will be generated based on the following VHDL code by Quartus II synthesizer? Thanks. /****VHDL code begins****/ entity con_0 is port ( c...
Altera_Forum's avatar
Altera_Forum
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14 years ago

The same 'circuit' as the statement

cout<="0101";

i.e., it will generate cout with a static value.

If that static value goes nowhere, then the synthesis tool will delete it. If however cout is used, for example cout is tied to pins on the FPGA, then Quartus will keep the signal.

Use the RTL viewer to see what the 'circuit' looks like.

Cheers,

Dave