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I was leaning more to outcome# 2, because the FPGA might fail to meet timing (i.e where the set_input_delay max would exceed the Setup Relationship but this is not reflected in TimeQuest since it is not constrained) resulting in hardware failure. Is my assumption here valid?
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since internal paths are constrained then there is no issue there.
The io paths are not constrained and are unknown. The compiler ends up with figures for tSU/tH/tCO at io as achieved by fitter. Whether this is good for your io or not is a different matter. Moreover from build to build it will change. So it is not recommended anyway. If you are not sure about io constraints try some arbitrary figures rather than leave it unconstrained.
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