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Altera_Forum
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10 years ago

Question about unconstrained input/ouput paths

Let's say I do not specify any input/output constraints in my design (set_input_delay/set_output_delay). This means there is nothing to report 'to the input register' as well as 'from the output regi...
Altera_Forum's avatar
Altera_Forum
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10 years ago

I was leaning more to outcome# 2, because the FPGA might fail to meet timing (i.e where the set_input_delay max would exceed the Setup Relationship but this is not reflected in TimeQuest since it is not constrained) resulting in hardware failure. Is my assumption here valid?