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Let's say I do not specify any input/output constraints in my design (set_input_delay/set_output_delay). This means there is nothing to report 'to the input register' as well as 'from the output register'. What will happen in real hardware situation?
1) Hardware will fail as these paths are supposed to be timing-analyzed but is not due to the missing I/O constraints.
2) Hardware will not fail - but fitter might not optimize timing due to the absence of the I/O constraints.
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default behavior is that you will get a chip with a given tSU/tH/tCO which you shouldn't then violate i.e. external chips should take care.
This is no good as fitting may also vary from build to build.
Honored Contributor
