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Altera_Forum's avatar
Altera_Forum
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10 years ago

Question about unconstrained input/ouput paths

Let's say I do not specify any input/output constraints in my design (set_input_delay/set_output_delay). This means there is nothing to report 'to the input register' as well as 'from the output regi...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

just make assignmet for ports "Virtual Pin"

it is closer to 2nd, but it is not true. Cause you constrain clock network at least and exclude asynchronus signals properly from analysis. Try out clock as Virtual :-P