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Thanks for the explanation. So in summary, synchronous de-assertion is not really necessary for Altera's devices since it has already been taken care in rec/rem. Only those that do not have async reset port will benefit from it. Do correct me if my understanding is incorrect.
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wrong. That is what you did by having double synchrinoser. The reset is termed synchronised (or what I call pre-synchronised and applied either way). I think you assume the case of wiring to async port as async, well it is locally but the incoming signal is pre-synchronised so that it doesn't de-assert anytime at will by controlled by clock edge.
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