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Altera_Forum
Honored Contributor
Honored ContributorQuestion about sync/async reset and recovery/removal
I understand most of the recommendation when implementing reset scheme is using asynchronous assertion and synchronous deassertion. My question is why do we need sync deassertion given that it is alr...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- The Q2 output can be connected either to the async register port(Altera recommends and saves resource) or applied through D input(Xilinx prefers, wastes resource). In either case the reset signal must be presynchronised to help achieve recovery/removal if applied async or setup/hold if applied through D input. --- Quote End --- Thanks for the explanation. So in summary, synchronous de-assertion is not really necessary for Altera's devices since it has already been taken care in rec/rem. Only those that do not have async reset port will benefit from it. Do correct me if my understanding is incorrect.
