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I understand this part, but again it is resetting the asynchronous part of the registers. Will this be analyzed as setup/hold or recovery/removal. If the latter, shouldn't it be considered asynchronous? My understanding is synchronous reset should be going through the D input of the registers.
Thanks.
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The Q2 output can be connected either to the async register port(Altera recommends and saves resource) or applied through D input(Xilinx prefers, wastes resource).
In either case the reset signal must be presynchronised to help achieve recovery/removal if applied async or setup/hold if applied through D input.
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