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If reset is not pre-synchronised it means it will be be de-asserted anytime and so it will fail timing. In fact Timequest cannot report on a path unless it is between two registers (including outside io registers).
The output of double synchroniser is synchronised since it is the D input that matters here.
D1 starts and stays as '1' from powerup then
when reset is de-asserted i.e. changes '0'=> '1' Q1 changes from '0' => '1' ( on clock edge but de-assertion can be at any time relative to clock edge) then
Q2 changes from '0' to '1' on next clock edge while reset has been '1' for one clock period.
Q2 is then used as reset for the system registers.
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Does Q2 feed to the registers' aclr port of the rest system? I mean Q2 is used as async reset in HDL coding?
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