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Altera_Forum's avatar
Altera_Forum
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12 years ago

Question about Quartus Compilation

Hi everyone I am working on a FPGA project using Stratix ii family. When compiling my project, the software automatically using DSP block to map some parts of the project. Now I do not want th...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

The only options I know of are:

1. Use a bigger device.

2. Modify your algorithm.

Are you sure you havent accidently set the limits of the DSP blocks to fewer than the device has, having played with the settings.