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Altera_Forum
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12 years ago

Question about Quartus Compilation

Hi everyone I am working on a FPGA project using Stratix ii family. When compiling my project, the software automatically using DSP block to map some parts of the project. Now I do not want th...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

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That doesnt really make much sense. The other design obviously uses components that are not suitable for a DSP block. This one does, which is a good thing. DSP blocks are there to be used. Comparing logic for logic is not really that helpful.

Just say that the first design uses 0 DSPs and this one uses N.

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Thanks Tricky

Now here comes another problem, the Compilation says the number of DSP blocks the project needs is much larger than the FPGA core has. what shall I do now?