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Altera_Forum
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12 years ago

Question about Quartus Compilation

Hi everyone I am working on a FPGA project using Stratix ii family. When compiling my project, the software automatically using DSP block to map some parts of the project. Now I do not want th...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

I think the multipliers are generated by the megawizard cause I used a lot of Arithmetic IP in megawizard such as ALTFP_DIV, ALTFP_EXP and so on.

As I mentioned in another thread(which is replied by you.Thanks again Tricky), I just want to compare two Algorithm's hardware consumption. Because one of them,when I do compilation, does not consume DSP block, while the other one does. Then I think is there any method to ban the DSP block when compilation,only to use the register and LUT.