Altera_ForumHonored Contributor12 years agoQuestion about Quartus Compilation Hi everyone I am working on a FPGA project using Stratix ii family. When compiling my project, the software automatically using DSP block to map some parts of the project. Now I do not want th...Show More
Altera_ForumHonored Contributor12 years agoYou also might want to set "maximum DSP block usage" to 0.
Recent DiscussionsInterfacing Avalon Streaming FIFO IP with GTS Ethernet Hard IPInvalid license key (inconsistent authentication code)Regarding the issue of UFM not startingram retimingReset Release IP for Agilex needs Stratix 10 device files installed!