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JensVkb's avatar
JensVkb
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

questa_fse cannot simulate design: Module not found

I created a design in which my own custom Avalon MM Master sends commands to the On-chip Flash Intel FPGA IP csr interface, which is an Avalon MM Slave. In this design the Dual Configuration Intel FP...
JensVkb's avatar
JensVkb
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

@YEan That did the trick indeed. I was relying on the automatically created .do file, but that one probably does not compile the IP files and hence cannot execute them. The main point of difference is sourcing the msim_setup.tcl file and calling the dev_com and com commands.

I could now simulate my dummy test project containing only one IP core. I'll now apply this for my real projects!

For future readers: these steps are also detailed in https://www.intel.com/content/www/us/en/docs/programmable/691278/21-3/quick-start.html , which I seem to have missed when starting my simulation process, hence leading to this agony.

PS: the link in step 2 detailed above, gives an "Access Denied".