QuartusII and Hardware implementation of Code

Hello All!

I am interesting in hardware implementation of my VHDL code - for example I wrote

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architecture arch1 of summx1 is

begin

process (A,B)

begin

if (A='0' and B='0') then

Summ <='0';

Carry <='0';

elsif (A='0' and B='1') then

Summ <='1';

Carry <='0';

elsif (A='1' and B='0') then

Summ <='1';

Carry <='0';

else -- A=1 and B=1

Summ <='0';

Carry <='1';

end if;

end process;

end arch1;

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and

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architecture arch2 of summx1 is

begin

Summ <= A xor B;

Carry <= A and B;

end arch2;

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it is implementation of 1-bit counter with carry.

I looked at RTL - it makes different schematic for differnt architecture, like I understand it will be different imlementation and in logic elements in PLD?

Also I am interesting why it makes different schematic implementation evet if I turn ON smart compilation? 2nd is more easier- have 2 components in RTL - not like 1-st - a lot of components..

How I can look what implementation will be for each architecture - look at hardware logic in PLD - I use EPM3128A.

I attach files for RTL and Technology Map Viewer(I don`t understand clearly nw wha it is..)