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- Altera_Forum
Honored Contributor
open the VHDL file in quartus. Make sure the source code is added to the project file list.
goto File -> Create/update -> Create symbol file. Then in your top level BDF double click anywhere and now your modules should be available to place in the BDF. NOTE: You cannot simulate BDF files directly. You have to either convert them to HDL or compile them for a (slow) netlist simulation. The best option is just to make the whole design HDL.