New ContributorQuartus warning RES-50005
Hello.
I am getting the following warning during the Quartus flow:
RES-50005 - RAM Control Signals Driven by Flip-Flops with Asynchronous Clears
I am not sure I understand why this is a problem.
In our design all FFs have an 'asynchronous reset' which toggles with the power-up/down of the chip. As usual, the reset is activated asynchronously and deactivated synchronously.
Can anybody give me explain to me the reason why this warning could be an issue?
I am presuming the message in this and your other post are from the Design Assistant, not the Quartus compiler. The Design Assistant checks that you are following best practices in your design. You don't have to fix the issues found by the Design Assistant, but it's a good idea to review them and possibly act on them.
My guess for this message is your target device is a Stratix 10 or Agilex with Hyperflex. As such, you want to try to avoid using asynchronous resets as much as possible to allow for more retiming opportunities into the hyper-registers by the hyper-retimer stage of the compiler.
