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Aswathi
New Contributor
New ContributorQuartus: Timing analysis
Hi Team,
I wrote a verilog code of an FSM in Moore model. Timing analyser identified one of the states as a clock. There are some combinational blocks , the input parameters of the combinational bl...
sstrell
Super Contributor
Super ContributorCan you provide the HDL code for the state machine and your .sdc file? It's hard to figure out what's going on without this info.
