Quartus Router Congestion

I think that's the Hard PCIe block. Strange it shows up as routing congestion but not sure if I've looked at that or not. In the messages, where is the area of most congestion?

Besides Fitter Aggressive Routability, I would suggest turning up the Placement Effort to 8(More Fitter Settings) and create a quartus.ini with the following:

vpr_placement_effort_targets_all_edges = on

This will make your compile time go up, but basically makes the placer spend more timing making moves that make the design get better timing AND make it more routable(without the .ini it just does the former). This might work, but you may be too congested. To be honest, reducing the logic a bit is probably your best bet in that case. Unless there's something explicitly wrong with the floorplan the fitter chooses, manually floorplanning doesn't really help.

I also find it strange that 14% of your ALMs are lost due to LAB input limits. I don't look at the number much but I believe it's because that line item is usually a really small percentage. That basically means your LABs have the maximum number of signals coming into them, which basically means they require the maximum amount of required routing to get to them, i.e. not only are you using a lot of resources, your design is naturally tough to route. (This is one of those things that doesn't jump out of the raw numbers. You could build a shift register that uses 100% of the ALMs and Quartus would have no problem routing it, but a cross-bar mux would be significantly more difficult.)

One last thing to try, if you're using a more recent version of Quartus(I forget which, maybe Q15.0 and beyond), but try Fitter -> More Settings -> Advanced Physical Optimizations, which is a different algorithm that is supposed to improve routability.

Good luck, as fixing no routes is not easy.