Quartus-Qsys-BSP issue

I have a design that contains 2 instantiations of a DDR3 controller. Once controller is connected to the NiosII via an Avalon MM bridge (NiosII-->Avalon.MM.Bridge-->Uniphy DDR3 controller) and the other Uniphy DDR3 controller is connected to the same NiosII via a custom IP block that I have designed. The Custom IP block has a slave interface that is connected to the NiosII processor and a Master output that is connected to the other DDR3 controller. The problem that I see is that the first DDR3 controller shows up in the list of memory devices when I use the Qsys generate button, generate a testbench system and then bring up my application using NiosII Eclipse in Modelsim simulations. In the BSP editor/Linker script/Linker region name, I see the first DDR3 listed and therefore I can load my design into it by selecting it and then generating the BSP package, and have the NiosII processor that is connected to the Avalong-MM-Pipeline-Bridge execute it.

However in the same BSP editor/Linker script/Linker region name neither my custom IP block nor the DDR3 that is connected to it show up. Therefore I can not load my application into the second DDR3 memory and have the NiosII processor execute it.

The strange thing is that I can write/read to this same DDR3 using a program executed on the NiosII processor. So the Qsys generated system is functional.

Has anyone seen this sort of problem before?

Any help to resolve this issue will be greatly appreciated.

Thanks