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New ContributorQuartus Prime (Verilog) Error (10200): Verilog HDL Conditional Statement error
I desire to interface an FPGA to a 32-bit ADC. The serial clock to the ADC should be gated and only clock the ADC after the ADC has finished acquiring each sample. I am gating the serial clock by me...
Remove negedge busy from the always_ff sensitivity list, and add logic tests for busy == 1'b0 in the appropriate if statements to only clock the data on posedge clk when busy is low, else hold data otherwise.
You are telling Quartus that data can change on either posedge clk or negedge busy which can't happen for a single clock flipflop.
