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New Contributor

5 years ago

Quartus Prime Pro Edition 27x 27 multiplier

Hi guys, I'm new in Quartus. Had the first verilog code tested as below under Agilex device : AGFB014R24A2E2VR0. module sync_unsigned_27x27mul (out, clk, a, b); output [53:0] out; input clk; ...

SyafieqS

Super Contributor

5 years ago

Hi Beng,

To target the dedicated DSP block architecture in Intel FPGA devices. there are recommended HDL coding styles. you may refer to link below related to Inferring Multipliers and DSP Functions(pg5).

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-qpp-design-recommendations.pdf

Thanks,

Regards

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Quartus Prime Pro Edition 27x 27 multiplier

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