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TowerLy's avatar
TowerLy
Icon for New Contributor rankNew Contributor
5 years ago

Quartus Prime Pro and Questasim

Hi,

I use Quartus Prime Pro and Questasim. I have a basic design that has two modules (counter and PLL IP). After Analysis and Elaboration -> Generate Simulator Script for IP, I open Questasim and enter necessary commands to transcript as mentioned in ug-qpp-tp-simulation.pdf. Simulation starts, modules are seen but there is no signal for visibility. For full visibility, I enter "vopt" command but Questasim gave an error that fourteennm_clk_divider.v in PLL IP is not defined. What is wrong that I made?

2 Replies

  • EngWei_O_Intel's avatar
    EngWei_O_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    5 years ago

    Hi Samet Caglan

    Can you share us the design or at least the design files with issue and the script that you set up?

    Thanks.

    Eng Wei

    • EngWei_O_Intel's avatar
      EngWei_O_Intel
      Icon for Frequent Contributor rankFrequent Contributor
      4 years ago

      Hi

      We do not receive any response from you to the previous reply that have been provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

      Eng Wei